An Optimizing Framework on MLIR for Efficient FPGA-based Accelerator Generation

With the increasing demand for computing capability given limited resourceand power budgets, it is crucial to deploy applications to customizedaccelerators like FPGAs. However, FPGA programming is non-trivial. Althoughexisting high-level synthesis (HLS) tools improve productivity to a certainextent, they are limited in scope and capability to support sufficientFPGA-oriented optimizations. This paper focuses on FPGA-based accelerators andproposes POM, an optimizing framework built on multi-level intermediaterepresentation (MLIR). POM has several features which demonstrate its scope andcapability of performance optimization. First, most HLS tools dependexclusively on a single-level IR to perform all the optimizations, introducingexcessive information into the IR and making debugging an arduous task. Incontrast, POM introduces three layers of IR to perform operations at suitableabstraction levels, streamlining the implementation and debugging process andexhibiting better flexibility, extensibility, and systematicness. Second, POMintegrates the polyhedral model into MLIR, enabling advanced dependenceanalysis and various FPGA-oriented loop transformations. By representing nestedloops with integer sets and maps, loop transformations can be conductedconveniently through manipulations on polyhedral semantics. Finally, to furtherrelieve design effort, POM has a user-friendly programming interface (DSL) thatallows a concise description of computation and includes a rich collection ofscheduling primitives. An automatic design space exploration (DSE) engine isprovided to search for high-performance optimization schemes efficiently andgenerate optimized accelerators automatically. Experimental results show thatPOM achieves a $6.46\times$ average speedup on typical benchmark suites and a$6.06\times$ average speedup on real-world applications compared to thestate-of-the-art.