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Power Optimized Divide-By-2/3 Counter Based Clock Design Using Multiplexer
Author(s) -
M Anandkumar.
Publication year - 2013
Publication title -
iosr journal of engineering
Language(s) - English
Resource type - Journals
eISSN - 2278-8719
pISSN - 2250-3021
DOI - 10.9790/3021-03151422
Subject(s) - multiplexer , computer science , power (physics) , telecommunications , electrical engineering , multiplexing , physics , quantum mechanics , engineering

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