Open AccessClock gating for low power circuit design by Merge and split methods
Author(s) -
K. Hariharan
Publication year - 2012
Publication title -
iosr journal of engineering
Language(s) - English
Resource type - Journals
eISSN - 2278-8719
pISSN - 2250-3021
DOI - 10.9790/3021-0204577581
Subject(s) - computer science , clock gating , merge (version control) , power gating , gating , electrical engineering , clock skew , parallel computing , clock signal , telecommunications , voltage , transistor , neuroscience , jitter , engineering , biology