Open AccessImplementation of the Binary Multiplier on CPLD Using Reversible Logic Gates
Author(s) -
Rajender Kumar
Publication year - 2017
Publication title -
iosr journal of electronics and communication engineering
Language(s) - English
Resource type - Journals
eISSN - 2278-8735
pISSN - 2278-2834
DOI - 10.9790/2834-1201034042
Subject(s) - complex programmable logic device , computer science , binary number , multiplier (economics) , arithmetic , logic gate , parallel computing , computer hardware , algorithm , mathematics , economics , macroeconomics