Open AccessDesign and implementation of 16 X 16 Truncated multiplier with different families of Xilinx
Author(s) -
Deepshikha Bharti,
Nisha Laguri
Publication year - 2014
Publication title -
iosr journal of electronics and communication engineering
Language(s) - English
Resource type - Journals
eISSN - 2278-8735
pISSN - 2278-2834
DOI - 10.9790/2834-09335760
Subject(s) - computer science , multiplier (economics) , field programmable gate array , arithmetic , computer architecture , parallel computing , embedded system , mathematics , economics , macroeconomics