Open AccessDesign of High Speed Reconfigurable Coprocessor for Multiplier/Adder and Subtractions Operations
Author(s) -
S Mallikarjunaswamy
Publication year - 2012
Publication title -
iosr journal of electronics and communication engineering
Language(s) - English
Resource type - Journals
eISSN - 2278-8735
pISSN - 2278-2834
DOI - 10.9790/2834-0241015
Subject(s) - adder , coprocessor , computer science , multiplier (economics) , field programmable gate array , parallel computing , arithmetic , computer hardware , embedded system , latency (audio) , telecommunications , mathematics , economics , macroeconomics