Open AccessA Systematic Approach to Reduce Wirebond defects caused by Tight Wire Loop Profile on Ball Grid Array Packages
Author(s) -
Irish Beltran,
Mark Anthony Ramiro,
Jerome J. Dinglasan
Publication year - 2022
Publication title -
journal of engineering research and reports
Language(s) - English
Resource type - Journals
ISSN - 2582-2926
DOI - 10.9734/jerr/2022/v22i217522
Subject(s) - ball grid array , wire bonding , die (integrated circuit) , grid , integrated circuit packaging , product (mathematics) , computer science , engineering , automotive engineering , electronic engineering , reliability engineering , mechanical engineering , integrated circuit , electrical engineering , materials science , chip , mathematics , soldering , geometry , composite material
Wirebond quality aspects on a semiconductor manufacturing is one of the key factors to be considered in having a robust product. Certain criteria are defined, met, and affects the output on the product. Other variables from downstream process are also taken in account to affect the response, specific die position or placement on die attach is one example. Without controlling this input factor, unwanted out of specification response will occur and may result to rejections on the next process. This paper will focus on how to address the wire tight loop on wire bond process by analyzing the problem through systematic approach using statistical tools improving the current performance of die placement on BGA products.