Open AccessEnhanced Wirebonding Technique on QFN Device with Critical Die Reference
Author(s) -
Jonathan C. Pulido,
Frederick Ray I. Gomez
Publication year - 2021
Publication title -
journal of engineering research and reports
Language(s) - English
Resource type - Journals
ISSN - 2582-2926
DOI - 10.9734/jerr/2021/v20i317283
Subject(s) - wire bonding , quad flat no leads package , integrated circuit packaging , die (integrated circuit) , electronic packaging , ball (mathematics) , integrated circuit , fiducial marker , computer science , reliability engineering , electronic engineering , engineering , manufacturing engineering , mechanical engineering , electrical engineering , materials science , chip , artificial intelligence , nanotechnology , mathematics , mathematical analysis , adhesive , layer (electronics)
Wirebonding is one of the most challenging assembly manufacturing processes in semiconductor packaging industry. This paper discussed the wirebonding challenge and the solution to mitigate misplaced ball issues and prevent pattern recognition alignment errors. Parameter optimization particularly on wirebond looping was done to ensure that the silicon die’s L-fiducial is visible and not obstructed by the wires, which is the operator point or die reference of the unit during wirebonding setup. Ultimately, the optimized wirebonding parameter prevented the pattern recognition alignment error and misplaced ball issues during the lot process. For future works, the configuration and technique could be applied on packages with the similar situation.