Open AccessDie Placement Advancement for Prevention of Silhouetted Die Occurrence on LGA Package
Author(s) -
Rennier S. Rodriguez,
Frederick Ray I. Gomez,
Edwin M. Graycochea
Publication year - 2021
Publication title -
journal of engineering research and reports
Language(s) - English
Resource type - Journals
ISSN - 2582-2926
DOI - 10.9734/jerr/2021/v20i217270
Subject(s) - die (integrated circuit) , enhanced data rates for gsm evolution , integrated circuit packaging , engineering , process (computing) , computer science , mechanical engineering , integrated circuit , electrical engineering , telecommunications , operating system
In semiconductor packaging industry, silhouetted die defect is occasionally encountered in singulation process esp. on substrate land grid array (LGA) package with tight clearances. This paper is focused on the prevention of the silhouetted die occurrence as it would affect the assembly yield performance of the device. The silhouetted die is caused by the tight clearance of die edge to package edge, given the machine and process tolerances. Process enhancement and optimization were done through adjusting the die placement accordingly as per the defined measurement. Eventually, the occurrence of silhouetted die was successfully mitigated by formulating the appropriate die placement references.