Open AccessSemiconductor Package Design Solution for Addressing High-Density Configuration
Author(s) -
Rennier S. Rodriguez,
Frederick Ray I. Gomez,
Maiden Grace R. Maming
Publication year - 2020
Publication title -
journal of engineering research and reports
Language(s) - English
Resource type - Journals
ISSN - 2582-2926
DOI - 10.9734/jerr/2020/v16i317166
Subject(s) - miniaturization , materials science , substrate (aquarium) , silicon , integrated circuit , integrated circuit packaging , wire bonding , optoelectronics , plating (geology) , semiconductor , electrical engineering , nanotechnology , engineering , chip , oceanography , geophysics , geology
The direction for integrated circuit (IC) packaging is getting smaller yet with increasing unit performance. In this case substrate-based technology became limited to miniaturization and downsizing direction. In this paper, a specialized design of IC is presented and discussed through augmentation of routing channels at the backside of the silicon die to eliminate the substrate application in the package. Routed channels are fabricated using plating or immersion process that are electrically connected to the bonding pads through conductive via within the silicon material. By eliminating the substrate re-distribution layers (RDL), a package is expected to decrease by 20 – 40% from its designed dimension.