Open AccessEffect of Backgrinding Tape Lamination on Die Alignment
Author(s) -
Bryan Christian S. Bacquian,
Frederick Ray I. Gomez
Publication year - 2020
Publication title -
journal of engineering research and reports
Language(s) - English
Resource type - Journals
ISSN - 2582-2926
DOI - 10.9734/jerr/2020/v14i417129
Subject(s) - wafer dicing , lamination , wafer , die (integrated circuit) , miniaturization , die preparation , integrated circuit , wafer testing , materials science , grinding , mechanical engineering , engineering drawing , electrical engineering , optoelectronics , engineering , nanotechnology , layer (electronics)
The continuing growth and development on semiconductor package miniaturization have become a particular interest and focus semiconductor industry. The importance of thinner packages also demands a thinner vertical structure of the integrated circuit (IC) design with silicon die or the wafer playing essential role in package thinning. As the wafer goes thinner, problems may occur in the wafer preparation or pre-assembly. With the introduction of new wafer preparation technologies such as dicing before grinding and laser die attach film (DAF) cut, technical challenges were inevitable. The paper focused on the effect of backgrinding tape lamination on die alignment. Tensionless lamination helped eliminate the horizontal pressure applied into the tape thus mitigating the die mis-alignment problem. For future works, the configuration could be applied on wafers with similar technology and/or application.