Open AccessVariable latency L1 data cache architecture design in multi-core processor under process variation
Author(s) -
Joon Ho Kong
Publication year - 2015
Publication title -
han-guk keompyuteo jeongbo hakoe nonmunji/han'gug keompyuteo jeongbo haghoe nonmunji
Language(s) - Uncategorized
Resource type - Journals
eISSN - 2383-9945
pISSN - 1598-849X
DOI - 10.9708/jksci.2015.20.9.001
Subject(s) - cache algorithms , cache invalidation , cache , smart cache , cache pollution , computer science , cache coloring , page cache , parallel computing , mesi protocol , latency (audio) , cpu cache , telecommunications