Open AccessVariable latency L1 data cache architecture design in multi-core processor under process variation
Author(s) -
Joonho Kong
Publication year - 2015
Publication title -
journal of the korea society of computer and information
Language(s) - Uncategorized
Resource type - Journals
eISSN - 2383-9945
pISSN - 1598-849X
DOI - 10.9708/jksci.2015.20.9.001
Subject(s) - cache algorithms , cache invalidation , cache , smart cache , cache pollution , computer science , cache coloring , page cache , parallel computing , mesi protocol , latency (audio) , cpu cache , telecommunications
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