Open AccessFPGA-based systolic deconvolution architecture for upsampling
Author(s) -
Alex Noel Joseph Raj,
Lianhong Cai,
Wei Li,
Zhemin Zhuang,
Tardi Tjahjadi
Publication year - 2022
Publication title -
peerj computer science
Language(s) - Uncategorized
Resource type - Journals
ISSN - 2376-5992
DOI - 10.7717/peerj-cs.973
Subject(s) - computer science , upsampling , kernel (algebra) , adder , field programmable gate array , systolic array , digital signal processing , parallel computing , deconvolution , convolution (computer science) , algorithm , computer hardware , computational science , very large scale integration , embedded system , mathematics , image (mathematics) , telecommunications , combinatorics , artificial intelligence , machine learning , artificial neural network , latency (audio)
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