Open AccessStack-through silicon via dynamic power consumption optimization in three-dimensional integrated circuit
Author(s) -
Gang Dong,
Wu Wen-Shan,
Yintang Yang
Publication year - 2015
Publication title -
wuli xuebao
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.199
H-Index - 47
ISSN - 1000-3290
DOI - 10.7498/aps.64.026601
Subject(s) - stack (abstract data type) , reduction (mathematics) , dynamic demand , through silicon via , computer science , power (physics) , three dimensional integrated circuit , materials science , power consumption , electronic engineering , integrated circuit , silicon , optoelectronics , engineering , physics , quantum mechanics , geometry , mathematics , programming language
Stack-through silicon via (TSV) used in three-dimensional integrated circuit has good temperature and heat transfer characteristics. A novel model for optimizing the dynamic power consumption based on stacked-TSV is proposed in this paper, in which delay, area and minimum aperture are comprehensively considered. After extracting single TSV parasitic electrical parameters, we analyze the influences of TSV size on multilayer TSV power consumption and delay performance, thereby building the hierarchical reduction TSV structure step by step. Moreover, the influences of TSV height and thickness of oxide layer are discussed. Results show that the model can significantly improve the dynamic power consumption at the expense of little delay. The power consumption optimization reduction is up to 19.52% with 5% delay penalty.