Open AccessMechanism and optimal design of a high-k dielectric conduction enhancement SOI LDMOS
Author(s) -
Xiaowei Wang,
Luo Xiaorong,
YinKai Chao,
Fan Yuan-Hang,
Kun Zhou,
Fan Ye,
Cai Jin-Yong,
Luo Yin-Chun,
Bo Zhang,
Zhaoji Li
Publication year - 2013
Publication title -
acta physica sinica
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.199
H-Index - 47
ISSN - 1000-3290
DOI - 10.7498/aps.62.237301
Subject(s) - ldmos , materials science , silicon on insulator , dielectric , thermal conduction , optoelectronics , breakdown voltage , electric field , dielectric strength , substrate (aquarium) , voltage , condensed matter physics , silicon , electrical engineering , composite material , physics , quantum mechanics , engineering , oceanography , geology
A high-k dielectric conduction enhancement SOI LDMOS is proposed and investigated by simulation. The high-k dielectric pillars are located at sidewalls of the drift region. The high-k dielectric assists the self-adapted depletion in the drift region, reshapes the electric field distribution, and makes the three-dimensional RESURF effect realized in a high-voltage blocking state. Dependences of the breakdown voltage (VB) and the specific on-resistance (Ron,sp) on device parameters are exhibited using three-dimensional simulation. Simulation results show that the proposed structure increases VB by 16%–18% and decreases Ron.sp by 13%–20%, compared with the conventional super-junction SOI LDMOS. Furthermore, the charge-imbalance caused by the substrate-assisted depletion effect is alleviated.
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