Open AccessA compact model of substrate resistance for deep sub-micron gate grounded NMOS electrostatic discharge protection device
Author(s) -
Wu Xiao-Peng,
Yong Yang,
Gao H,
Gang Dong,
Changchun Chai
Publication year - 2013
Publication title -
wuli xuebao
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.199
H-Index - 47
ISSN - 1000-3290
DOI - 10.7498/aps.62.047203
Subject(s) - nmos logic , materials science , substrate (aquarium) , optoelectronics , electrostatic discharge , ldmos , computer science , breakdown voltage , voltage , electrical engineering , transistor , oceanography , geology , engineering
The current controlled voltage source model of substrate parasitic resistance of deep sub-micron electrostatic discharge protection device is optimized by considering the effect of conductance modulation. A compact macro-model of substrate resistance is presented according to the characteristics of lightly doped bulk substrate and heavily doped substrate with a lightly doped epitaxial layer, which is scalable with the layout dimension. The experimental model parameters of devices with various spaces between source and substrate diffusion can be extracted by device simulation. The breakdown behavior of gate grounded negative-channel metal oxide semiconductor shows the effectiveness of this method. In the meantime, the simulation time-consuming of the compact model is only 7% that of the device simulation software.