Open AccessThreshold voltage analytical model for strained Si SOI MOSFET with high-k dielectric
Author(s) -
李劲,
刘红侠,
李斌,
曹磊,
袁博
Publication year - 2010
Publication title -
wuli xuebao
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.199
H-Index - 47
ISSN - 1000-3290
DOI - 10.7498/aps.59.8131
Subject(s) - silicon on insulator , threshold voltage , mosfet , materials science , dielectric , high κ dielectric , doping , optoelectronics , silicon , voltage , drain induced barrier lowering , condensed matter physics , electrical engineering , transistor , physics , engineering
A strained Si fully depleted SOI MOSFET,which has the advantages of strained Si,high-k gate and SOI structure, is presented in this paper. A two-dimensional analytical model for the threshold voltage in strained Si fully depleted SOI MOSFET with high-k dielectric is proposed by solving Possions equation. Several important parameters are taken into account in the model. Relationships between threshold voltage,Ge Profile and thickness of strained silicon are investigated. The result shows that the threshold voltage decreases with Ge Profile and strained silicon thickness increasing. Relationships between threshold voltage,dielectric constant of high k gate and doping conceration of strained silicon are also investigated. The result shows that the threshold voltage increases with dielectric constant of high-k and doping conceration of strained silicon increasing. SCE and DIBL are analyzed finally,which also demonstrate that this novel device can suppress SCE and DIBL effect greatly.