Open AccessStudy on clock skew of unsymmetrical RLC interconnect tree with temperature distribution
Author(s) -
Wang Zeng,
Gang Dong,
Yintang Yang,
Jianwei Li
Publication year - 2010
Publication title -
wuli xuebao
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.199
H-Index - 47
ISSN - 1000-3290
DOI - 10.7498/aps.59.5646
Subject(s) - rlc circuit , interconnection , inductance , skew , clock skew , electronic engineering , distribution (mathematics) , process (computing) , computer science , materials science , topology (electrical circuits) , electronic circuit , electrical engineering , mathematics , clock signal , engineering , capacitor , mathematical analysis , voltage , telecommunications , operating system
Based on the influence of the nonuniform temperature distribution and the inductance effect of the wires on the interconnect delay time, a zero-clock-skew construction method of RLC interconnect clock tree is presented in this paper. The proposed analytical model has closed form expression and takes temperature distribution, inductance effect and unsymmetrical interconnect structure into consideration. Adopting parameters of 65 nm process technology, the proposed model is compared with the other available similar models. Results show that the new model is more accurate with maximum 1% error.