Open AccessA compact interconnect temperature distribution model considering the via effect and the heat fringing effect
Author(s) -
Zhu Zhangming,
Hao Bao-Tian,
Qian Libo,
Bo Zhong,
Yintang Yang
Publication year - 2009
Publication title -
wuli xuebao
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.199
H-Index - 47
ISSN - 1000-3290
DOI - 10.7498/aps.58.7130
Subject(s) - interconnection , materials science , dielectric , cmos , optoelectronics , back end of line , insulator (electricity) , thermal conductivity , electronic engineering , computer science , composite material , telecommunications , engineering
Considering the via effect and the heat fringing effect simultaneouslywe proposed a compact interconnect temperature distribution model that can be applied for single interconnect and multilevel interconnects. Based on the 65 nm complementary metal-oxide semiconcluctor CMOS interconnect and material parameterthe temperature distribution of multilevel interconnects and single interconnect with different lengths was calculated. The results show that the temperature rise of global interconnect is still large when the via effect is consideredwhile the temperature rise of intermediate line and local line is quite small. For multilevel interconnectsthe temperature rise in the uppermost layer interconnect is the largest. The temperature rise is approximately proportional to the thickness of insulatorand will rise higher if the thermal conductivity of dielectric materials becomes smaller. The proposed interconnect temperature distribution model can be used in nanometer CMOS computer-aided design.