Open AccessCharacteristics of degradation under GIDL stress in ultrathin gate oxide LDD nMOSFET’s
Author(s) -
Haifeng Chen,
Hao Yue,
Xiaohua Ma,
Tang Yu,
Meng Zhiqin,
Yanrong Cao,
Zhou Peng-Ju
Publication year - 2007
Publication title -
wuli xuebao
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.199
H-Index - 47
ISSN - 1000-3290
DOI - 10.7498/aps.56.1662
Subject(s) - materials science , degradation (telecommunications) , threshold voltage , stress (linguistics) , leakage (economics) , oxide , logarithm , gate oxide , mosfet , optoelectronics , transistor , voltage , electrical engineering , metallurgy , mathematical analysis , linguistics , philosophy , mathematics , economics , macroeconomics , engineering
The threshold voltage (VTH) degradation have been investigated under GIDL (gate induced drain leakage) stresse in LDD nMOSFET with 1.4 nm-thick gate oxide. The trapped holes and interface states generated in the stress process at interface around LDD overlapping region result in the increase in VTH. The logarithm of VTH degradation after GIL stresses at constant VDG is proportional to the ratio of VD/VDG. The VTH degradation after GIDL stresses at constant VD increases with increasing VG in the stress, and that after GIDL stresses at constant VG increases with increasing VD in the stress In the last two cases the VTH degradation is always linear with the reciprocal of the bias which changes in the stress, and the absolute values of degradation slopes are 0.76 and 13.5, respectively. Experimental result shows that the degradation depends more strongly on VD than on VG.