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Design of Dual loop PLL with low noise characteristic
Author(s) -
Young-Shig Choi,
Sungjin Ahn
Publication year - 2016
Publication title -
the journal of the korean institute of information and communication engineering
Language(s) - English
Resource type - Journals
eISSN - 2288-4165
pISSN - 2234-4772
DOI - 10.6109/jkiice.2016.20.4.819
Subject(s) - phase locked loop , dual loop , delay locked loop , phase margin , loop (graph theory) , phase noise , bandwidth (computing) , cmos , control theory (sociology) , voltage controlled oscillator , pll multibit , electronic engineering , loop gain , transfer function , computer science , voltage , engineering , mathematics , electrical engineering , telecommunications , control (management) , operational amplifier , combinatorics , artificial intelligence , amplifier

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