Open AccessHardware Acceleration of Sparse Support Vector Machines for Edge Computing
Author(s) -
Vuk Vranjković,
Rastislav Struharik
Publication year - 2020
Publication title -
elektronika ir elektrotechnika
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.224
H-Index - 26
eISSN - 2029-5731
pISSN - 1392-1215
DOI - 10.5755/j01.eie.26.3.25796
Subject(s) - pruning , support vector machine , computer science , field programmable gate array , memory footprint , enhanced data rates for gsm evolution , acceleration , throughput , hardware acceleration , footprint , field (mathematics) , parallel computing , hardware architecture , gate array , computer engineering , computer hardware , artificial intelligence , mathematics , telecommunications , paleontology , physics , software , classical mechanics , pure mathematics , agronomy , wireless , biology , programming language , operating system
In this paper, a hardware accelerator for sparse support vector machines (SVM) is proposed. We believe that the proposed accelerator is the first accelerator of this kind. The accelerator is designed for use in field programmable gate arrays (FPGA) systems. Additionally, a novel algorithm for the pruning of SVM models is developed. The pruned SVM model has a smaller memory footprint and can be processed faster compared to dense SVM models. In the systems with memory throughput, compute or power constraints, such as edge computing, this can be a big advantage. The experiments on several standard datasets are conducted, which aim is to compare the efficiency of the proposed architecture and the developed algorithm to the existing solutions. The results of the experiments reveal that the proposed hardware architecture and SVM pruning algorithm has superior characteristics in comparison to the previous work in the field. A memory reduction from 3 % to 85 % is achieved, with a speed-up in a range from 1.17 to 7.92.