Open AccessArchitectural Exploration of an FPGA-based Hardware Accelerator for the Gaussian Filter using Approximate Computing
Author(s) -
Guilherme A. M. Sborz,
Felipe Viel,
Cesar Albenes Zeferino
Publication year - 2020
Language(s) - English
Resource type - Conference proceedings
DOI - 10.5753/sbesc_estendido.2020.13111
Subject(s) - field programmable gate array , computer science , hardware acceleration , scalability , reconfigurable computing , implementation , computer architecture , embedded system , computer hardware , image processing , acceleration , image (mathematics) , artificial intelligence , database , programming language , physics , classical mechanics
The growing use of computer vision applications has increased the demand for efficient image processing implementations. These applications have constraints that, in some cases, can only be met by dedicated hardware implementations. This work presents architectures that apply approximate computing techniques to improve efficiency and scalability for implementing digital image filters on FPGA. These architectures were implemented as hardware accelerators for an embedded processor in an FPGA-based System-on-Chip. The results show that the use of approximate computing techniques can reduce costs without affecting results for the target application, which is an essential feature for further acceleration using parallel processing on hardware.