Open AccessDesign of Carry Select Adder using BEC and Common Boolean Logic
Author(s) -
Syed Mustafaa M,
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Mr.M.V. Sathish,
S Nivedha,
Magribatul Noora A K,
Safrin Sifana T,
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AUTHOR_ID,
AUTHOR_ID,
AUTHOR_ID
Publication year - 2022
Publication title -
indian journal of vlsi design
Language(s) - English
Resource type - Journals
ISSN - 2582-8843
DOI - 10.54105/ijvlsid.c1205.031322
Subject(s) - adder , computer science , arithmetic , power (physics) , carry save adder , carry (investment) , power consumption , binary number , parallel computing , mathematics , telecommunications , physics , finance , quantum mechanics , economics , latency (audio)
Carry Select Adder (CSLA) is known to be the fastest adder among the conventional adder structure, which uses multiple narrow adders. CSLA has a great scope of reducing area, power consumption, speed and delay. From the structure of regular CSLA using RCA, it consumes large area and power. This proposed work uses a simple and dynamic Gate Level Implementation which reduces the area, delay, power and speed of the regular CSLA. Based on a modified CSLA using BEC the implementation of 8-b, 16-b, 32-b square root CSLA (SQRT CSLA) architecture have been developed. In order to reduce the area and power consumption in a great way we proposed a design using binary to excess 1 converter (BEC). This paper proposes an dynamic method which replaces a BEC using Common Boolean Logic.