Open AccessDesign and Evaluation of a 32-bit Carry Select Adder using 4-bit Hybrid CLA Adder
Author(s) -
Muhammad Saddam Hossain,
Farhadur Arifin
Publication year - 2021
Publication title -
the aiub journal of science and engineering
Language(s) - English
Resource type - Journals
eISSN - 2520-4890
pISSN - 1608-3679
DOI - 10.53799/ajse.v20i2.119
Subject(s) - adder , carry save adder , 4 bit , carry (investment) , computer science , serial binary adder , arithmetic , cadence , 16 bit , cmos , bit (key) , 32 bit , 8 bit , computer hardware , power–delay product , electronic circuit , electronic engineering , mathematics , electrical engineering , engineering , computer security , finance , economics
Adder circuits play a remarkable role in modern microprocessor. Adders are widely used in critical paths of arithmetic operation such as multiplication and subtraction. A Carry Select Adder (CSA) design methodology using a modified 4-bit Carry Look-Ahead (CLA) Adder has been proposed in this research. The proposed 4-bit CLA used hybrid logic style based logic circuits for Carry Generate (Gi) and Carry Propagate (Pi) functions in order to improve performance and reduce the number of transistor used. The modified 4-bit CLA is used as the basic unit for implementation of 32-bit CSA. The proposed design of hybrid CLA based 32-bit CSA has been compared with conventional static CMOS based 32-bit CSA and 32-bit Ripple Cary Adder (RCA) by conducting simulation using Cadence Virtuoso. Power consumption and delay in the proposed 32-bit CSA found 322.6 (uW) and 0.556 (ns) whereas power and delay in the conventional 32-bit CSA was 455.4 (uW) and 0.667 (ns) respectively. We have done all the simulation using Cadence Virtuoso 90 nm tool.