Open AccessDesign of efficient DSP operation with 16x16 RMAC unit using cadence tool
Author(s) -
Leo Pauline,
U. Megovia,
C. Selvapriya,
P. Gowmari
Publication year - 2022
Publication title -
international journal of health sciences (ijhs) (en línea)
Language(s) - English
Resource type - Journals
eISSN - 2550-6978
pISSN - 2550-696X
DOI - 10.53730/ijhs.v6ns1.5956
Subject(s) - computer science , adder , accumulator (cryptography) , multiplier (economics) , computer hardware , electronic circuit , digital signal processing , electrical engineering , latency (audio) , algorithm , telecommunications , engineering , economics , macroeconomics
Reversible multiplier and accumulator (RMAC) are the essential operation using in DSP application where DSP processor requires high performance with different application.so the speed of operation is increased only by, implementing and designing 16x16 RMAC. Since the power consumption and heat is high in MAC. It can only be reduced by using an RMAC and chips like FPGA get increases. Whereas three fetch decode-execute cycle is needed in MAC for simulation of result.so time delay and high quantum cost should be contained in circuit. Though single fetch-decode execute cycle is more enough to RMAC for simulation of result. Time delay were not required and quantum cost is low for the circuit. For long circuits using normal gates dissipates more heat. The operations performed by using reversible gates do not dissipate heat energy because the circuit reaches the input as well as output. In this reversible MAC, the gates, adder is reversible. Accumulator uses Fredkin gates. If single bit of information is lost, it diss-appear (kTln2) joules of heat energy for irreversible circuit. No more information mapping is lost in reversible circuits between input and output. It deals with VLSI design and FPGA technology.