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Design of Asynchronous Viterbi Decoder using Dual-Rail Protocol for Low power consumption
Author(s) -
Nupur R. Chambhare,
Surekha Tadse Kalambe
Publication year - 2015
Publication title -
journal of advance research in mechanical and civil engineering
Language(s) - English
Resource type - Journals
ISSN - 2208-2379
DOI - 10.53555/nnmce.v2i3.352
Subject(s) - computer science , asynchronous communication , viterbi decoder , viterbi algorithm , idle , handshake , asynchronous system , handshaking , decoding methods , embedded system , computer hardware , clock signal , real time computing , computer network , synchronous circuit , telecommunications , jitter , operating system
Paper shows the review of asynchronous Viterbi decoder using hand shake protocol as Dual – Rail protocol. Viterbi decoders are used for decoding convolution forward error correction codes in a large proportion of digital transmission systems including mobile phones and digital television. For portable applications, the battery size and lifetime is of commercial importance as is the size of the electronics. The approach adopted in the Viterbi design is to use a self-timed (or asynchronous) timing strategy. This saves power through not having to generate or distribute a global clock. Instead, timing between blocks is performed by local handshake signals. This enables an asynchronous system to only consume power when doing useful work and to have an idle power of near zero. Furthermore, there is an inherent advantage to asynchronous systems in that a system can switch almost instantaneously between the idle state and maximum activity; this is much more difficult to organize in a clocking system.

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