Open AccessEnergy Efficient Quaternary Capacitive DAC Switching Scheme for SAR -ADC
Author(s) -
Sarvesh S. Chavhan,
K. M. Bogawar
Publication year - 2015
Publication title -
journal of advance research in electrical and electronics engineering
Language(s) - English
Resource type - Journals
ISSN - 2208-2395
DOI - 10.53555/nneee.v2i6.191
Subject(s) - successive approximation adc , cmos , capacitive sensing , computer science , digital to analog converter , energy (signal processing) , electronic engineering , energy consumption , interface (matter) , electrical engineering , engineering , capacitor , voltage , physics , bubble , quantum mechanics , maximum bubble pressure method , parallel computing
This paper presents energy efficient 4-bit successive approximation register analog to digital converter (SAR-ADC) for neural recording front end interface of neural prosthetic system(Brain machine interface). The energy efficient quaternary capacitive switching scheme (QCS) in the implementation of capacitive digital to analog converter (C-DAC) is employed which makes the energy consumption in the C-DAC independent of the output digital code. The proposed quaternary capacitive technique in C-DAC achieves a 50% reduction in the average energy consumption. The design is implemented in 0.25um standard complementary metal-oxide semiconductor technology (CMOS).