Open AccessOptimization Simulation programming for NoC
Author(s) -
Dhafer Sabah Yaseen
Publication year - 2020
Publication title -
iraqi journal for computer science and mathematics
Language(s) - English
Resource type - Journals
eISSN - 2958-0544
pISSN - 2788-7421
DOI - 10.52866/ijcsm.2019.01.01.003
Subject(s) - multiprocessing , computer science , network on a chip , workload , network topology , computer architecture , software , torus , dimension (graph theory) , mesh networking , embedded system , parallel computing , distributed computing , computer network , operating system , geometry , mathematics , pure mathematics , wireless
The article presents the concept of networks-on-chip (NoCs) as a promising alternative to communication subsystem for multiprocessor systems with bus architecture. The networks simulator developed as important software tool to estimate NoC performance parameters. The results of approbation of the developed simulator are reliance of the number of hops on the NoC dimension for mesh and torus topologies, as well as the dependences of communication links workload on the frequency, with which IP blocks generate messages. Its possibilities are considered and the accepted results are given.