Open AccessDESIGN OF FLOATING POINT MULTIPLIER BASED ON BOOTH ALGORITHM USING VHDL
Author(s) -
Ms. Anuja A. Bhat* Prof. Mangesh N. Thakare
Publication year - 2017
Publication title -
zenodo (cern european organization for nuclear research)
Language(s) - English
DOI - 10.5281/zenodo.572573
Subject(s) - vhdl , booth's multiplication algorithm , computer science , multiplier (economics) , floating point , algorithm , arithmetic , parallel computing , mathematics , computer hardware , adder , field programmable gate array , telecommunications , economics , macroeconomics , latency (audio)
In this paper, we have presented of High Speed, low power and less delay 32-bit IEEE 754 Floating Point Subtractor and Multiplier using Booth Multiplier. Multiplication is an important fundamental function in many Digital Signal Processing (DSP) applications such as Fast Fourier Transform (FFT). Since multiplication dominates the execution time of most DSP algorithms, so there is a need of high speed multiplier. The main objective of this research is to reduce delay, power and to increase the speed. The coding is done in VHDL, synthesis and simulation has been done using Xilinx ISE simulator. The modules designed are 24-bit Booth Multiplier for mantissa multiplication in Floating Point Multiplier, 32-bit Floating Point Subtractor and 32-bit Floating Point Multiplier. The Computational delay obtained by Floating Point Subtractor, booth multiplier and floating point multiplier is 16.180nsec, 33.159nsec and 18.623nsec respectivel