Open AccessPHYSICAL DESIGN, LAYOUT AND SIMULATION USING C5 PROCESS TECHNOLOGY OF 8 BIT ARITHMETIC AND LOGIC UNIT
Author(s) -
Rita Jain Dr. R. P. Singh Aparna Gupta*
Publication year - 2018
Publication title -
zenodo (cern european organization for nuclear research)
Language(s) - English
DOI - 10.5281/zenodo.1325039
Subject(s) - arithmetic , bit (key) , computer science , unit (ring theory) , process (computing) , arithmetic logic unit , 4 bit , computer hardware , electronic engineering , mathematics , engineering , programming language , cmos , mathematics education , computer security