z-logo
open-access-imgOpen Access
High-Performance Design of a 4-Bit Carry Look-Ahead Adder in Static CMOS Logic
Author(s) -
Mehedi Hasan,
Abdul Hasib Siddique,
Abdal Haque Mondol,
Mainul Hossain,
Hasan U. Zaman,
Sharnali Islam
Publication year - 2020
Publication title -
indonesian journal of electrical engineering and informatics (ijeei)
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.168
H-Index - 8
ISSN - 2089-3272
DOI - 10.52549/ijeei.v8i4.2582
Subject(s) - adder , cmos , carry (investment) , power–delay product , electronic engineering , computer science , 4 bit , cadence , propagation delay , serial binary adder , logic gate , critical path method , computer hardware , engineering , systems engineering , finance , economics

The content you want is available to Zendy users.

Already have an account? Click here to sign in.
Having issues? You can contact us here
Accelerating Research

Address

John Eccles House
Robert Robinson Avenue,
Oxford Science Park, Oxford
OX4 4GP, United Kingdom