Open AccessEffect of clock gating in conditional pulse enhancement flip-flop for low power applications
Author(s) -
Kuruvilla John,
Vinod Kumar R. S.,
S. S. Kumar
Publication year - 2019
Publication title -
indonesian journal of electrical engineering and informatics (ijeei)
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.168
H-Index - 8
ISSN - 2089-3272
DOI - 10.52549/ijeei.v7i2.1041
Subject(s) - flip flop , clock gating , electronic engineering , flops , power gating , power (physics) , cmos , computer science , pulse width modulation , idle , engineering , electrical engineering , clock signal , clock skew , voltage , transistor , physics , quantum mechanics , parallel computing , jitter , operating system
Accelerating Research
Robert Robinson Avenue,
Oxford Science Park, Oxford
OX4 4GP, United Kingdom
Address
John Eccles HouseRobert Robinson Avenue,
Oxford Science Park, Oxford
OX4 4GP, United Kingdom