z-logo
open-access-imgOpen Access
Low Power Square Root Carry Select Adder Using AVLS-TSPC-Based D Flip-Flop
Author(s) -
P. Siddaiah,
Nikhil Kiran Jayanthi,
Samana Hanumanth Managoli
Publication year - 2021
Publication title -
electrica
Language(s) - Uncategorized
Resource type - Journals
SCImago Journal Rank - 0.148
H-Index - 2
ISSN - 2619-9831
DOI - 10.5152/electr.2021.21024
Subject(s) - flip flop , flip , carry (investment) , adder , square root , arithmetic , power (physics) , square (algebra) , computer science , parallel computing , mathematics , telecommunications , physics , chemistry , economics , enhanced data rates for gsm evolution , biochemistry , apoptosis , geometry , finance , quantum mechanics , latency (audio)

The content you want is available to Zendy users.

Already have an account? Click here to sign in.
Having issues? You can contact us here