Open AccessA Built-in Self-Test System for External DRAM
Author(s) -
Gor A. Abgaryan
Publication year - 2020
Publication title -
mathematical problems of computer science
Language(s) - English
Resource type - Journals
eISSN - 2738-2788
pISSN - 2579-2784
DOI - 10.51408/1963-0061
Subject(s) - dram , dynamic random access memory , computer science , embedded system , reliability (semiconductor) , semiconductor memory , built in self test , static random access memory , computer hardware , integrated circuit , universal memory , electronic circuit , reliability engineering , memory refresh , computer memory , engineering , electrical engineering , operating system , power (physics) , physics , quantum mechanics
In the fast-growing Integrated Circuits (IC) industry, memory is one of the few keys to have systems with improved and fast performance. Only one transistor and a capacitor are required for Dynamic Random-Access Memory (DRAM) bit. It is widely used for mass storage. Although the high-efficiency tests are performed to provide the reliability of the memories, maintaining acceptable yield and quality is still the most critical task. To perform a high-speed effective test of DRAM memories, a built-in self-test (BIST) mechanism is proposed.