Open AccessDesign of High Efficiency Two Stage Power Amplifier in 0.13µM RF CMOS Technology for 2.4GHZ WLAN Application
Author(s) -
Shridhar Sahu,
Deshmukh A.Y
Publication year - 2013
Publication title -
international journal of vlsi design and communication systems
Language(s) - English
Resource type - Journals
eISSN - 0976-1357
pISSN - 0976-1527
DOI - 10.5121/vlsic.2013.4404
Subject(s) - cmos , stage (stratigraphy) , amplifier , electrical engineering , rf power amplifier , electronic engineering , computer science , telecommunications , engineering , paleontology , biology
A two stage CMOS power amplifier is implemented in 0.13μm RF CMOS technology using ADS tooloperating at 2.4 GHz with dc supply of 2.5 V. Driver stage as the input stage and power stage as the outputstage are the two stages. A cascode topology is used in the driver stage and basic topology is used in thepower stage. Output power at 1dB compression point is 20.028 dBm and maximum output power deliveredby this circuit is 22.002 dBm. Power added efficiency calculated at 1 dB compression point is 44.669 %whereas the maximum power added efficiency comes out to be 70.196 %. The input return and outputreturn losses are -11.132 dB and -12.467 dB respectively. Isolation loss and small signal gain arecalculated to be -61.889 dB and 43.745 dB respectively. This circuit shows power gain of 42.728 dB at 1dBcompression point. The total dc current flowing through this circuit is 0.0901 A. MOSFET only biascircuits are used to reduce total dc current. This circuit is designed for application in WLAN