Performance Analysis of Modified QSERL Circuit

This work is based on a new approach for minimizing energy consumption in quasi static energy recoverylogic (QSERL) circuit which involves optimization by removing the non adiabatic losses completely.Energy recovering circuitry based on adiabatic principles is a promising technique leading towards lowpowerhigh performance circuit design. The efficiency of such circuits may be increased by reducing theadiabatic and non-adiabatic losses drawn by them during the charging and recovery operations. In thispaper, performance of the proposed logic style is analyzed and compared with CMOS in theirrepresentative inverters, gates, flip flops and adder circuits. All the circuits were simulated by VIRTUOSOSPECTRE simulator of Cadence in 0.18μm technology. In our proposed inverter the energy efficiency hasbeen improved to almost 30% & 20% upto 20MHz and 20fF external load capacitance in comparison toCMOS & QSERL circuits respectively. Our proposed circuit provides energy efficient performance up to100 MHz and thus it has proven to be used in high-performance VLSI circuitry