Open AccessArea Efficient 3.3GHZ Phase Locked Loop with Four Multiple Output Using 45NM VLSI Technology
Author(s) -
Ujwala A. Belorkar,
S. A. Ladhake
Publication year - 2011
Publication title -
international journal of vlsi design and communication systems
Language(s) - English
Resource type - Journals
eISSN - 0976-1357
pISSN - 0976-1527
DOI - 10.5121/vlsic.2011.2110
Subject(s) - very large scale integration , loop (graph theory) , computer science , phase locked loop , electronic engineering , phase (matter) , electrical engineering , engineering , mathematics , embedded system , physics , phase noise , combinatorics , quantum mechanics