Open AccessDIA-TORUS:A Novel Topology for Network on Chip Design
Author(s) -
Deewakar Thakyal,
Pushpita Chatterjee
Publication year - 2016
Publication title -
international journal of computer networks and communications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.159
H-Index - 8
eISSN - 0975-2293
pISSN - 0974-9322
DOI - 10.5121/ijcnc.2016.8310
Subject(s) - computer science , torus , chip , topology (electrical circuits) , network topology , computer architecture , computer network , telecommunications , mathematics , geometry , combinatorics
The shortcomings of conventional bus architectures are in terms of scalability and the ever increasing\uddemand of more bandwidth. And also the feature size of sub-micron domain is decreasing making it\uddifficult for bus architectures to fulfill the requirements of modern System on Chip (SoC) systems. Network\udon chip (NoC) architectures presents a solution to the earlier mentioned shortcomings by employing a\udpacket based network for inter IP communications. A pivotal feature of NoC systems is the topology in\udwhich the system is arranged. Several parameters which are topology dependent like hop count, path\uddiversity, degree and other various parameters affect the system performance. We propose a novel\udtopology forNoC architecture which has been thoroughly compared with the existing topologies on the\udbasis of different network parameters