Open AccessClock Gating Flip-Flop using Embedded XoR Circuitry
Author(s) -
Peiyi Zhao,
William Olarte Cortés,
Congyi Zhu,
Tom Springer
Publication year - 2021
Publication title -
computer science and information technology ( cs and it )
Language(s) - English
Resource type - Conference proceedings
DOI - 10.5121/csit.2021.110809
Subject(s) - flip flop , flops , computer science , clock gating , flip , gating , power consumption , power gating , power (physics) , xor gate , electronic engineering , logic gate , clock signal , cmos , parallel computing , voltage , electrical engineering , engineering , transistor , algorithm , telecommunications , clock skew , physics , apoptosis , chemistry , biology , physiology , biochemistry , quantum mechanics , jitter
Flip flops/Pulsed latches are one of the main contributors of dynamic power consumption. In this paper, a novel flip-flop (FF) using clock gating circuitry with embedded XOR, GEMFF, is proposed. Using post layout simulation with 45nm technology, GEMFF outperforms prior stateof-the-art flip-flop by 25.1% at 10% data switching activity in terms of power consumption.