Low Power-Area GDI & PTL Techniques Based Full Adder Designs | Zendy

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Low Power-Area GDI & PTL Techniques Based Full Adder Designs

Author(s) -

Karthik Reddy.G,

Kavita Khare

Publication year - 2013

Language(s) - Uncategorized

Resource type - Conference proceedings

DOI - 10.5121/csit.2013.3426

Subject(s) - computer science , adder , power (physics) , telecommunications , latency (audio) , physics , quantum mechanics

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