Open AccessArea Efficient Layout Design of CMOS Comparator using PTL Logic
Author(s) -
Jyoti Jyoti -,
Rajesh Mehra
Publication year - 2015
Publication title -
international journal of computer applications
Language(s) - English
Resource type - Journals
ISSN - 0975-8887
DOI - 10.5120/21784-5065
Subject(s) - comparator , computer science , cmos , computer architecture , electrical engineering , engineering , voltage