Open AccessAncient Indian Vedic Mathematics based 32-Bit Multiplier Design for High Speed and Low Power Processors
Author(s) -
Nishant G.Deshpande,
Rashmi Mahajan
Publication year - 2014
Publication title -
international journal of computer applications
Language(s) - English
Resource type - Journals
ISSN - 0975-8887
DOI - 10.5120/16742-6956
Subject(s) - multiplier (economics) , computer science , arithmetic , power (physics) , bit (key) , mathematics , computer security , physics , economics , macroeconomics , quantum mechanics
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