z-logo
open-access-imgOpen Access
An Algorithm for Leakage Power Reduction through IVC in CMOS VLSI Digital Circuits
Author(s) -
Manikya Vara Prasad Done,
Uday Panwar,
Kavita Khare
Publication year - 2014
Publication title -
international journal of computer applications
Language(s) - English
Resource type - Journals
ISSN - 0975-8887
DOI - 10.5120/16356-5740
Subject(s) - computer science , very large scale integration , leakage power , cmos , leakage (economics) , digital electronics , reduction (mathematics) , electronic circuit , algorithm , electronic engineering , electrical engineering , computer engineering , embedded system , transistor , voltage , mathematics , engineering , economics , macroeconomics , geometry

The content you want is available to Zendy users.

Already have an account? Click here to sign in.
Having issues? You can contact us here