Open AccessA Novel Power Reduction Technique for CMOS Circuits using Voltage Scaling and Transistor Gating
Author(s) -
Ankish Handa,
Prateek Garg,
Geetanjali Sharma
Publication year - 2014
Publication title -
international journal of computer applications
Language(s) - English
Resource type - Journals
ISSN - 0975-8887
DOI - 10.5120/16056-5301
Subject(s) - computer science , power gating , cmos , gating , transistor , scaling , reduction (mathematics) , electronic circuit , power (physics) , electrical engineering , leakage power , voltage , electronic engineering , physics , medicine , mathematics , engineering , geometry , quantum mechanics , physiology