Open AccessHigh Performance and Low Latency ECC Processor for Cryptography
Author(s) -
Mohan Rao Thokala
Publication year - 2021
Publication title -
international journal of advanced research in science, communication and technology
Language(s) - English
Resource type - Journals
ISSN - 2581-9429
DOI - 10.48175/ijarsct-v2-i3-304
Subject(s) - computer science , field programmable gate array , virtex , multiplier (economics) , elliptic curve cryptography , latency (audio) , cryptography , clock rate , embedded system , parallel computing , computer hardware , arithmetic , public key cryptography , encryption , mathematics , algorithm , operating system , chip , telecommunications , economics , macroeconomics
Elliptic curve cryptography processor implemented for point multiplication on field programmable gate array. Segmented pipelined full-precision multiplier is used to reduce the latency and also data dependency can be avoided by modifying Lopez-Dahab Montgomery PM Algorithm, results in drastic reduction in the number of clock cycles required. The proposed ECC processor is implemented on Xilinx FPGA families i.e. virtex-4, vitrtex-5, virtex-7.single and three multiplier based designs show the fastest performance compared with reported work individually. Our three multiplier based ECC processor implementation is taking the lowest number of clock cycles on FPGA based design processor.