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Design of Low Power Versatile Bit-Serial Multiplier in Finite Field GF (2m)
Author(s) -
Niveditha SR,
Brunda BS,
K Rohith,
R.V Nithyashree,
Mrs. Asha R
Publication year - 2022
Publication title -
international journal of advanced research in science communication and technology
Language(s) - English
Resource type - Journals
ISSN - 2581-9429
DOI - 10.48175/ijarsct-5848
Subject(s) - multiplier (economics) , verilog , 4 bit , finite field , computer science , arithmetic , very large scale integration , binary number , power analysis , cryptography , computer hardware , mathematics , embedded system , electronic engineering , field programmable gate array , cmos , algorithm , engineering , discrete mathematics , economics , macroeconomics

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