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Designing 10T SRAM for noise and Leakage Power Reduction using Stack Transistor Technique – A Review
Author(s) -
Miss. Seema S. Naik,
P. B. Patil
Publication year - 2022
Publication title -
international journal of advanced research in science communication and technology
Language(s) - English
Resource type - Journals
ISSN - 2581-9429
DOI - 10.48175/ijarsct-3520
Subject(s) - static random access memory , microprocessor , dram , cache , transistor , electronic engineering , computer science , cpu cache , sense amplifier , embedded system , semiconductor memory , computer hardware , engineering , electrical engineering , parallel computing , voltage

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