Open AccessDesign and Analysis of CMOS Full Adder
Author(s) -
Saurabh J. Shewale,
Sonal A Shirsath
Publication year - 2021
Publication title -
international journal of advanced research in science, communication and technology
Language(s) - English
Resource type - Journals
ISSN - 2581-9429
DOI - 10.48175/ijarsct-1902
Subject(s) - adder , computer science , cmos , microprocessor , nmos logic , computer hardware , electronic circuit , serial binary adder , electronic engineering , microcontroller , digital signal processing , very large scale integration , embedded system , electrical engineering , engineering , transistor , voltage
This paper presents a comparative study of Complementary MOSFET (CMOS) full adder circuits. Our approach is based on hybrid design full adder circuits combined in a single unit. Full adder circuit is an essential component for designing of various digital systems. It is used for different applications such as Digital signal processor, microcontroller, microprocessor and data processing units (DSP). In most of these systems the adder lies in the critical path that determines the overall speed of the system. Full adder is mainly used in VLSI devices like microprocessor for computational purposes. The proposed full adder cell has low power consumption, better area efficiency. Recently, there have been massive research interests in this area due to the growing need for low-power and high-performance computing systems. Our aim is to design and compare the full adder circuit in various technologies and compare their power capacity. By using the hybrid structure of NMOS and PMOS, we have implemented the circuit of full adder.