Open AccessVLSI Architecture for Designing a True Random Number Generator with Modified Parallel Run Length Encoding
Author(s) -
S Jayaram.,
G. Manavaalan,
S. Gunasekaran
Publication year - 2021
Publication title -
international journal of advanced research in science, communication and technology
Language(s) - English
Resource type - Journals
ISSN - 2581-9429
DOI - 10.48175/ijarsct-1017
Subject(s) - computer science , random number generation , encryption , cryptography , encoding (memory) , very large scale integration , pseudorandom number generator , computer hardware , parallel computing , embedded system , computer network , algorithm , artificial intelligence
The secured communication is a means to provide privacy and security for the data being transmitted. The cryptographic system has thus become a vital and inevitable platform for achieving data security in our day to day life ranging from the generation of one time passwords, session keys, signature parameters, ephemeral keys. The encryption level is entirely dependent on the unpredictability of the digital bit streams. The paper focuses on generating true random number sequences using hardware, so as to safeguard the encryption keys patterns for digital communications. These sequences are generated using purely digital components supported by an efficient VLSI architecture. The implementation of the proposed model is done using Mojo-V3, supported by Xilinx ISE software platform. The generated random sequences will further undergo some post processing operations, viz; Von-Neumann correction (VNC) and Parallel Run Length Encoding (PRLE), to eliminate the bias in bit stream and also to compensate the high power dissipation respectively.